Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data

This is my senior project, we aim to design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit.

⚡ A seamless integration of HuggingFace Transformers & Diffusers with RBLN SDK for efficient inference on RBLN NPUs.

PyTorch extension for Rebellions NPU

Rapid prototyping framework for deploying and evaluating ML models on hardware

T1C — Open-Source AI Accelerator Architecture. Like RISC-V did for CPUs, T1C does for AI chips. Fully open source, MIT Licensed.

Generate Spike extensions, assembly tests, SVA assertions & docs for custom RISC-V AI vector instructions from YAML specs. Bit-accurate FP8/BF16/INT4 numerics.

AS501 AI Semiconductor Design Basics & Practice Final Project

A QEMU-based PCIe device driver and userspace framework that simulates an AI accelerator with DMA and IRQ capabilities for educational purposes.

The Hyze IPU (Intelligence Processing Unit) is a revolutionary hardware-software co-design project aimed at redefining the efficiency and security of AI inference. Unlike traditional GPU-centric architectures, the Hyze IPU leverages a heterogeneous computing model that seamlessly integrates CPU, GPU, and a custom-built IPU into a single, AI chip

FORCE AI: Fast Optimization for Resource-Constrained Efficient AI Inference

A Kubernetes Device Plugin for Hailo AI accelerators, enabling seamless scheduling of AI inference workloads on edge devices like the Raspberry Pi AI HAT+.

Curated Edge AI resources for computer vision & audio: hardware, frameworks, benchmarks, literature, and communities (excluding mobile).

Double LLM inference speed of AX650N (M5Stack Module LLM) on CM3588 NAS. PCIe optimization toolkit with IRQ affinity + CPU governor tuning.

This project implements AXI-based matrix multiply accelerator.

INT8 Systolic-Array AI Accelerator on Zynq SoC with HW-SW Co-Design and Roofline Performance Analysis

A 4x4 Systolic Array TPU core co-created with Generative AI, featuring RTL to GDSII implementation on Sky130 process.

8x8 Systolic Array AI Accelerator - Non-pipelined single-cycle MAC PE Systolic array uses wave-skew dataflow for data movement between PEs

N*N systolic array multiplication using multiply and accumulate processing element