I am a Design Verification Engineer with hands-on experience in IP-level Verification, SystemVerilog/UVM, functional coverage, and formal verification (FRV/FPV).
I specialize in building scalable, reusable verification environments and debugging complex issues across RTL and gate-level simulations.

• 🎯 1+ year of experience across IP verification and UVM infrastructure at Synopsys
• 🧪 Expertise in: SystemVerilog, UVM, SV, SVA, Formal Verification, RTL Debug
• 🛠 Experienced with Synopsys VCS, Verdi, VC Formal
• 📚 Strong fundamentals in digital design, coverage-driven verification, and constrained-random testbenches
• 🌱 Currently deepening expertise in high-speed PHY/IP verification, memories and formal methods

Oct 2024 – Nov 2025 | Hyderabad

• Verified MIPI CD-PHY, focusing on high-speed camera/display interface functionality.
• Debugged complex bugs across RTL & GLS using Verdi.
• Performed functional + toggle coverage, closed coverage gaps, and improved test quality.
• Executed FRV/FPV on Testchip registers ensuring protocol correctness, access rules, and reset behavior.
• Collaborated with design teams to root-cause failures and refine verification plans.

Feb 2024 – Oct 2024 | Bangalore

• Completed industry-focused training in Digital Design, RTL coding, Synthesis, Linting, and UVM.
• Developed multiple RTL designs and corresponding SystemVerilog/UVM testbenches.
• Strengthened practical understanding of real-world verification challenges.

Dec 2023 – Jan 2024 | Remote

• Reviewed 300+ model-generated responses on Verilog, Digital Logic, and hardware fundamentals.
• Reported 50+ critical issues, improving technical correctness and safety of outputs.

• Tools: VCS, Verdi, VC Formal, SystemVerilog, UVM, SVA
• Performed RTL + GLS simulations, debugging edge-case issues.
• Executed FRV/FPV on registers, checking reset values, access permissions, and data integrity.
• Improved functional & toggle coverage by identifying missing scenarios.
• Coordinated with design teams to validate spec compliance.

• Tools: SystemVerilog, UVM, SVA, VCS, Verdi
• Verified FSM flow across ACTIVATE, READ, WRITE, and NOP sequences using assertions.
• Validated row/column/bank addressing and bus-to-SDRAM protocol mapping.
• Built a scoreboard-based data integrity checker for read/write correctness.

• Tools: SystemVerilog, UVM, SVA, VCS, Verdi
• Written driver and monitor logic according to the input and output protocol of AXI.
• Verified data transfers for different burst types (Fixed, Incrementing, Wrap)..
• Developed assertions & covergroups.

Languages:
SystemVerilog Verilog C++ Python

Verification Methodologies:
UVM Constrained Random Assertions (SVA) Functional Coverage Formal Verification (FRV/FPV)

Tools:
Synopsys VCS Verdi VC Formal Perforce Git Jira Linux

• PHY-level IP Verification
• Advanced UVM Techniques
• Formal Verification (FRV/FPV)
• High-speed interfaces & Memory protocols