HDLBits-Solutions

HDLBits is considered by many as the leetcode for HDL :) It is a repo of many circuit design exercises. I will capture my solutions in this repo. Feel free to snoop around and star the repo if it helped you in your HDL learning journey.

Table of Contents

1. Getting Started (2 Problems)

• 01_Getting_Started.v - Getting Started
• 02_Output_Zero.v - Output Zero

2. Verilog Language (41 Problems)

2.1 Basics (8 Problems)

• 03_Simple_Wire.v - Simple Wire
• 04_Four_Wires.v - Four Wires
• 05_Inverter.v - Inverter
• 06_AND_Gate.v - AND Gate
• 07_NOR_Gate.v - NOR Gate
• 08_XNOR_Gate.v - XNOR Gate
• 09_Declaring_Wires.v - Declaring Wires
• 10_7458_Chip.v - 7458 Chip

2.2 Vectors (9 Problems)

• 11_Vectors.v - Vectors
• 12_Vectors_In_More_Detail.v - Vectors in More Detail
• 13_Vector_Part_Select.v - Vector Part Select
• 14_Bitwise_Operators.v - Bitwise Operators
• 15_Four_Input_Gates.v - Four-Input Gates
• 16_Vector_Concatenation_Operator.v - Vector Concatenation Operator
• 17_Vector_Reversal_1.v - Vector Reversal 1
• 18_Replication_Operator.v - Replication Operator
• 19_More_Replication.v - More Replication

2.3 Modules (9 Problems)

• 20_Modules.v - Modules
• 21_Connecting_Ports_By_Position.v - Connecting Ports By Position
• 22_Connecting_Ports_By_Name.v - Connecting Ports By Name
• 23_Three_Modules.v - Three Modules
• 24_Modules_And_Vectors.v - Modules and Vectors
• 25_Adder_1.v - Adder 1
• 26_Adder_2.v - Adder 2
• 27_Carry_Select_Adder.v - Carry-Select Adder
• 28_Adder_Subtractor.v - Adder-Subtractor

2.4 Procedures (8 Problems)

• 29_Always_Blocks_Combinational.v - Always Blocks (Combinational)
• 30_Always_Blocks_Clocked.v - Always Blocks (Clocked)
• 31_If_Statement.v - If Statement
• 32_If_Statement_Latches.v - If Statement Latches
• 33_Case_Statement.v - Case Statement
• 34_Priority_Encoder.v - Priority Encoder
• 35_Priority_Encoder_With_Casez.v - Priority Encoder with Casez
• 36_Avoiding_Latches.v - Avoiding Latches

2.5 More Verilog Features (7 Problems)

• 37_Conditional_Ternary_Operator.v - Conditional Ternary Operator
• 38_Reduction_Operators.v - Reduction Operators
• 39_Reduction_Even_Wider_Gates.v - Reduction: Even Wider Gates
• 40_Combinational_For_Loop_Vector_Reversal_2.v - Combinational For-Loop: Vector Reversal 2
• 41_Combinational_For_Loop_255_Bit_Population_Count.v - Combinational For-Loop: 255-Bit Population Count
• 42_Generate_For_Loop_100_Bit_Binary_Adder_2.v - Generate For-Loop: 100-Bit Binary Adder 2
• 43_Generate_For_Loop_100_Digit_BCD_Adder.v - Generate For-Loop: 100-Digit BCD Adder

3. Circuits (86 Problems)

3.1 Combinational Logic (37 Problems)

3.1.1 Basic Gates (17 Problems)

• 44_Wire.v - Wire
• 45_GND.v - GND
• 46_NOR_Basic.v - NOR
• 47_Another_Gate.v - Another Gate
• 48_Two_Gates.v - Two Gates
• 49_More_Logic_Gates.v - More Logic Gates
• 50_7420_Chip.v - 7420 Chip
• 51_Truth_Tables.v - Truth Tables
• 52_Two_Bit_Equality.v - Two-Bit Equality
• 53_Simple_Circuit_A.v - Simple Circuit A
• 54_Simple_Circuit_B.v - Simple Circuit B
• 55_Combine_Circuits_A_And_B.v - Combine Circuits A and B
• 56_Ring_Or_Vibrate.v - Ring or Vibrate?
• 57_Thermostat.v - Thermostat
• 58_3_Bit_Population_Count.v - 3-Bit Population Count
• 59_Gates_And_Vectors.v - Gates and Vectors
• 60_Even_Longer_Vectors.v - Even Longer Vectors

3.1.2 Multiplexers (5 Problems)

• 61_2_To_1_Multiplexer.v - 2-to-1 Multiplexer
• 62_2_To_1_Bus_Multiplexer.v - 2-to-1 Bus Multiplexer
• 63_9_To_1_Multiplexer.v - 9-to-1 Multiplexer
• 64_256_To_1_Multiplexer.v - 256-to-1 Multiplexer
• 65_256_To_1_4_Bit_Multiplexer.v - 256-to-1 4-Bit Multiplexer

3.1.3 Arithmetic Circuits (7 Problems)

• 66_Half_Adder.v - Half Adder
• 67_Full_Adder.v - Full Adder
• 68_3_Bit_Binary_Adder.v - 3-Bit Binary Adder
• 69_Adder.v - Adder
• 70_Signed_Addition_Overflow.v - Signed Addition Overflow
• 71_100_Bit_Binary_Adder.v - 100-Bit Binary Adder
• 72_4_Digit_BCD_Adder.v - 4-Digit BCD Adder

3.1.4 Karnaugh Map to Circuit (8 Problems)

• 73_3_Variable.v - 3-Variable K-Map
• 74_4_Variable_1.v - 4-Variable K-Map 1
• 75_4_Variable_2.v - 4-Variable K-Map 2
• 76_4_Variable_3.v - 4-Variable K-Map 3
• 77_Minimum_SOP_And_POS.v - Minimum SOP and POS
• 78_Karnaugh_Map_1.v - Karnaugh Map 1
• 79_Karnaugh_Map_2.v - Karnaugh Map 2
• 80_K_Map_Implemented_With_A_Multiplexer.v - K-Map Implemented With A Multiplexer

3.2 Sequential Logic (49 Problems)

3.2.1 Latches and Flip-Flops (18 Problems)

• 81_D_Flip_Flop.v - D Flip-Flop
• 82_D_Flip_Flops.v - D Flip-Flops
• 83_DFF_With_Reset.v - DFF with Reset
• 84_DFF_With_Reset_Value.v - DFF with Reset Value
• 85_DFF_With_Asynchronous_Reset.v - DFF with Asynchronous Reset
• 86_DFF_With_Byte_Enable.v - DFF with Byte Enable
• 87_D_Latch.v - D Latch
• 88_DFF_1.v - DFF 1
• 89_DFF_2.v - DFF 2
• 90_DFF_Plus_Gate.v - DFF+Gate
• 91_Mux_And_DFF_1.v - Mux and DFF 1
• 92_Mux_And_DFF_2.v - Mux and DFF 2
• 93_DFFs_And_Gates.v - DFFs and Gates
• 94_Create_Circuit_From_Truth_Table.v - Create Circuit From Truth Table
• 95_Detect_An_Edge.v - Detect an Edge
• 96_Detect_Both_Edges.v - Detect Both Edges
• 97_Edge_Capture_Register.v - Edge Capture Register
• 98_Dual_Edge_Triggered_Flip_Flop.v - Dual-Edge Triggered Flip-Flop

3.2.2 Counters (8 Problems)

• 99_Four_Bit_Binary_Counter.v - Four-Bit Binary Counter
• 100_Decade_Counter.v - Decade Counter
• 101_Decade_Counter_Again.v - Decade Counter Again
• 102_Slow_Decade_Counter.v - Slow Decade Counter
• 103_Counter_1_12.v - Counter 1-12
• 104_Counter_1000.v - Counter 1000
• 105_4_Digit_Decimal_Counter.v - 4-Digit Decimal Counter
• 106_12_Hour_Clock.v - 12-Hour Clock

3.2.3 Shift Registers (9 Problems)

• 107_4_Bit_Shift_Register.v - 4-Bit Shift Register
• 108_Left_Right_Rotator.v - Left/Right Rotator
• 109_Left_Right_Arithmetic_Shift_By_1_Or_8.v - Left/Right Arithmetic Shift by 1 or 8
• 110_5_Bit_LFSR.v - 5-Bit LFSR
• 111_3_Bit_LFSR.v - 3-Bit LFSR
• 112_32_Bit_LFSR.v - 32-Bit LFSR
• 113_Shift_Register_1.v - Shift Register 1
• 114_Shift_Register_2.v - Shift Register 2
• 115_3_Input_LUT.v - 3-Input LUT

3.2.4 More Circuits (4 Problems)

• 116_Cellular_Automata.v - Cellular Automata
• 117_Rule_90.v - Rule 90
• 118_Rule_110.v - Rule 110
• 119_Conway_Game_Of_Life_16x16.v - Conway's Game of Life 16x16

3.2.5 Finite State Machines (33 Problems)

• 120_Simple_FSM_1_Asynchronous_Reset.v - Simple FSM 1 (Asynchronous Reset)
• 121_Simple_FSM_1_Synchronous_Reset.v - Simple FSM 1 (Synchronous Reset)
• 122_Simple_FSM_2_Asynchronous_Reset.v - Simple FSM 2 (Asynchronous Reset)
• 123_Simple_FSM_2_Synchronous_Reset.v - Simple FSM 2 (Synchronous Reset)
• 124_Simple_State_Transitions_3.v - Simple State Transitions 3
• 125_Simple_One_Hot_State_Transitions_3.v - Simple One-Hot State Transitions 3
• 126_Simple_FSM_3_Asynchronous_Reset.v - Simple FSM 3 (Asynchronous Reset)
• 127_Simple_FSM_3_Synchronous_Reset.v - Simple FSM 3 (Synchronous Reset)
• 128_Design_A_Moore_FSM.v - Design a Moore FSM
• 129_Lemmings_1.v - Lemmings 1
• 130_Lemmings_2.v - Lemmings 2
• 131_Lemmings_3.v - Lemmings 3
• 132_Lemmings_4.v - Lemmings 4
• 133_One_Hot_FSM.v - One-Hot FSM
• 134_PS_2_Packet_Parser.v - PS/2 Packet Parser
• 135_PS_2_Packet_Parser_And_Datapath.v - PS/2 Packet Parser and Datapath
• 136_Serial_Receiver.v - Serial Receiver
• 137_Serial_Receiver_And_Datapath.v - Serial Receiver and Datapath
• 138_Serial_Receiver_With_Parity_Checking.v - Serial Receiver with Parity Checking
• 139_Sequence_Recognition.v - Sequence Recognition
• 140_Q8_Design_A_Mealy_FSM.v - Q8: Design a Mealy FSM
• 141_Q5a_Serial_Twos_Complementer_Moore_FSM.v - Q5a: Serial Two's Complementer (Moore FSM)
• 142_Q5b_Serial_Twos_Complementer_Mealy_FSM.v - Q5b: Serial Two's Complementer (Mealy FSM)
• 143_Q3a_FSM.v - Q3a: FSM
• 144_Q3b_FSM.v - Q3b: FSM
• 145_Q3c_FSM_Logic.v - Q3c: FSM Logic
• 146_Q6b_FSM_Next_State_Logic.v - Q6b: FSM Next-State Logic
• 147_Q6c_FSM_One_Hot_Next_State_Logic.v - Q6c: FSM One-Hot Next-State Logic
• 148_Q6_FSM.v - Q6: FSM
• 149_Q2a_FSM_1.v - Q2a: FSM 1
• 150_Q2b_One_Hot_FSM_Equations.v - Q2b: One-Hot FSM Equations
• 151_Q2a_FSM_Variant_2.v - Q2a: FSM (Variant 2)
• 152_Q2b_Another_FSM.v - Q2b: Another FSM

3.3 Building Larger Circuits (7 Problems)

• 153_Counter_With_Period_1000.v - Counter with Period 1000
• 154_4_Bit_Shift_Register_And_Down_Counter.v - 4-Bit Shift Register and Down Counter
• 155_FSM_Sequence_1101_Recognizer.v - FSM: Sequence 1101 Recognizer
• 156_FSM_Enable_Shift_Register.v - FSM: Enable Shift Register
• 157_FSM_The_Complete_FSM.v - FSM: The Complete FSM
• 158_The_Complete_Timer.v - The Complete Timer
• 159_FSM_One_Hot_Logic_Equations.v - FSM: One-Hot Logic Equations

4. Verification: Reading Simulations (15 Problems)

4.1 Finding Bugs in Code (5 Problems)

• 160_Mux.v - Mux
• 161_NAND.v - NAND
• 162_Mux_Variant_2.v - Mux (Variant 2)
• 163_Add_Sub.v - Add/Sub
• 164_Case_Statement.v - Case Statement

4.2 Build a Circuit from a Simulation Waveform (10 Problems)

• 165_Combinational_Circuit_1.v - Combinational Circuit 1
• 166_Combinational_Circuit_2.v - Combinational Circuit 2
• 167_Combinational_Circuit_3.v - Combinational Circuit 3
• 168_Combinational_Circuit_4.v - Combinational Circuit 4
• 169_Combinational_Circuit_5.v - Combinational Circuit 5
• 170_Combinational_Circuit_6.v - Combinational Circuit 6
• 171_Sequential_Circuit_7.v - Sequential Circuit 7
• 172_Sequential_Circuit_8.v - Sequential Circuit 8
• 173_Sequential_Circuit_9.v - Sequential Circuit 9
• 174_Sequential_Circuit_10.v - Sequential Circuit 10

5. Verification: Writing Testbenches (5 Problems)

• 175_Clock.v - Clock
• 176_Testbench1.v - Testbench1
• 177_AND_Gate_Testbench.v - AND Gate Testbench
• 178_Testbench2.v - Testbench2
• 179_T_Flip_Flop.v - T Flip-Flop

How to Use

1. Navigate to the appropriate category directory
2. Open the Verilog file matching the problem you want to solve
3. Each file contains:
   • Problem description in comments
   • Module definition with I/O ports
   • Complete or template implementation

Contributing

Feel free to suggest improvements or corrections to the solutions.