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Fetch SPI multi-lane support from upstream#3158

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machschmitt wants to merge 27 commits intoanalogdevicesinc:mainfrom
machschmitt:main-spi-multi-lane
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Fetch SPI multi-lane support from upstream#3158
machschmitt wants to merge 27 commits intoanalogdevicesinc:mainfrom
machschmitt:main-spi-multi-lane

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@machschmitt machschmitt commented Feb 27, 2026

PR Description

Fast-forward (or fast-backward?) SPI multi-lane support to ADI Linux.
To minimize the amount of merge conflicts, some updates that preceded SPI multi-lane were also included. Most relevant ones are:

  • "dt-bindings: iio: adc: add ADI ad4030, ad4630 and ad4632" which may be merged separately through Fetch ad4030 driver from upstream #3154.
  • "spi: Use inclusive language" which does several changes scattered through many parts of SPI core.
  • Jonas Gorski's patch set which provides better tracking of SPI peripheral number of CS lines.
  • "adi-axi-common: add version check function" containing new utility function to compare ADI AXI IP core versions.

Links to the lore are provided on the description of each patch.

PR Type

  • Bug fix (a change that fixes an issue)
  • New feature (a change that adds new functionality)
  • Breaking change (a change that affects other repos or cause CIs to fail)

PR Checklist

  • I have conducted a self-review of my own code changes
  • I have compiled my changes, including the documentation
  • I have tested the changes on the relevant hardware
  • I have updated the documentation outside this repo accordingly
  • I have provided links for the relevant upstream lore

Skallwar and others added 27 commits February 26, 2026 16:59
@Skallwar @machschmitt
dt-bindings: iio: adc: add ADI ad4030, ad4630 and ad4632
95ef9ff 
This adds a binding specification for the Analog Devices Inc. AD4030,
AD4630 and AD4632 families of ADCs.

- ad4030-24 is a 1 channel SAR ADC with 24 bits of precision and a
  sampling rate of 2M samples per second
- ad4032-24 is a 1 channel SAR ADC with 24 bits of precision and a
  sampling rate of 500K samples per second
- ad4630-16 is a 2 channels SAR ADC with 16 bits of precision and a
  sampling rate of 2M samples per second
- ad4630-24 is a 2 channels SAR ADC with 24 bits of precision and a
  sampling rate of 2M samples per second
- ad4632-16 is a 2 channels SAR ADC with 16 bits of precision and a
  sampling rate of 500K samples per second
- ad4632-24 is a 2 channels SAR ADC with 24 bits of precision and a
  sampling rate of 500K samples per second

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Esteban Blanc <eblanc@baylibre.com>
Link: https://patch.msgid.link/20250214-eblanc-ad4630_v1-v4-1-135dd66cab6a@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
@Skallwar @machschmitt
iio: adc: ad4030: add driver for ad4030-24
d9d2527 
This adds a new driver for the Analog Devices INC. AD4030-24 ADC.

The driver implements basic support for the AD4030-24 1 channel
differential ADC with hardware gain and offset control.

Signed-off-by: Esteban Blanc <eblanc@baylibre.com>
Link: https://patch.msgid.link/20250214-eblanc-ad4630_v1-v4-2-135dd66cab6a@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
@Skallwar @machschmitt
iio: adc: ad4030: add averaging support
3a5535b 
This add support for the averaging mode of AD4030 using oversampling IIO
attribute

Signed-off-by: Esteban Blanc <eblanc@baylibre.com>
Link: https://patch.msgid.link/20250214-eblanc-ad4630_v1-v4-3-135dd66cab6a@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
@Skallwar @machschmitt
iio: adc: ad4030: add support for ad4630-24 and ad4630-16
71fb50a 
AD4630-24 and AD4630-16 are 2 channels ADCs. Both channels are
interleaved bit per bit on SDO line.

Signed-off-by: Esteban Blanc <eblanc@baylibre.com>
Link: https://patch.msgid.link/20250214-eblanc-ad4630_v1-v4-4-135dd66cab6a@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
@Skallwar @machschmitt
iio: adc: ad4030: add support for ad4632-16 and ad4632-24
6835709 
AD4632-24 and AD4632-16 are 2 channels ADCs. Both channels are
interleaved bit per bit on SDO line.

Both of them do not have evaluation board. As such, the support added
here can't be tested. Support is provided as best effort until someone get
their hands on one.

Signed-off-by: Esteban Blanc <eblanc@baylibre.com>
Link: https://patch.msgid.link/20250214-eblanc-ad4630_v1-v4-5-135dd66cab6a@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
@Skallwar @machschmitt
docs: iio: ad4030: add documentation
317e986 
This adds a new page to document how to use the ad4030 ADC driver

Signed-off-by: Esteban Blanc <eblanc@baylibre.com>
Link: https://patch.msgid.link/20250214-eblanc-ad4630_v1-v4-6-135dd66cab6a@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
@machschmitt
ci: travis: add ad4030 to the exceptions lists
9f28488 
The ad4030 driver supports a subset of devices supported by ad4630.c.
Though, since the upstream ad4030 doesn't yet support all features
supported by ADI-only ad4630, no entry is added to ADI Kconfig. Only when
ad4030 become complete it will replace the ad4630 driver.

Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
@robherring @machschmitt
spi: Use of_property_present() for non-boolean properties
5644ea1 
The use of of_property_read_bool() for non-boolean properties is
deprecated in favor of of_property_present() when testing for property
presence.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20241104190759.277184-2-robh@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
@andy-shev @machschmitt
spi: Use inclusive language
2afad37 
Replace "master" by "[host] controller" in the SPI core code and comments.
All the similar to the "slave" by "target [device]" changes.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20250313140340.380359-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@KanjiMonster @machschmitt
spi: fix return code when spi device has too many chipselects
00e50bc 
Don't return a positive value when there are too many chipselects.

Fixes: 4d8ff6b ("spi: Add multi-cs memories support in SPI core")
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-2-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@andy-shev @machschmitt
spi: Group CS related fields in struct spi_device
3355b2a 
The CS related fields are sparse in the struct spi_device. Group them.
While at it, fix the comment style of cs_index_mask.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20250331103609.4160281-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@KanjiMonster @machschmitt
spi: keep track of number of chipselects in spi_device
df63e24 
There are several places where we need to iterate over a device's
chipselect. To be able to do it efficiently, store the number of
chipselects in spi_device, like we do for controllers.

Since we now use a device supplied value, add a check to make sure it
isn't more than we can support.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-3-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@KanjiMonster @machschmitt
spi: move unused device CS initialization to __spi_add_device()
f8f7529 
Using spi_device::num_chipselect, initialize unused device CS as invalid
at registration time in __spi_add_device(), and drop it from the
different allocation paths.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-4-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@KanjiMonster @machschmitt
spi: drop check for validity of device chip selects
0982850 
Now that we know the number of chip selects of a device, we can assume
these are valid, and do not need to check them first.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-5-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@KanjiMonster @machschmitt
spi: don't check spi_controller::num_chipselect when parsing a dt device
817c511 
Do not validate spi_controller::num_chipselect against SPI_CS_CNT_MAX
when parsing an spi device firmware node.

Firstly this is the wrong place, and this should be done while
registering/validating the controller. Secondly, there is no reason for
that check, as SPI_CS_CNT_MAX controls the amount of chipselects a
device may have, not a controller may have.

So drop that check as it needlessly limits controllers to SPI_CS_CNT_MAX
number of chipselects.

Likewise, drop the check for number of device chipselects larger than
controller's number of chipselects, as __spi_add_device() will already
catch that as either one of the chip selects will be out of range, or
there is a duplicate one.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-6-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@marckleinebudde @machschmitt
spi: Raise limit on number of chip selects to 24
6788a52 
We have a system which uses 24 SPI chip selects, raise the hard coded
limit accordingly.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://patch.msgid.link/20250629-spi-increase-number-of-cs-v2-1-85a0a09bab32@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
@KanjiMonster @machschmitt
spi: reduce device chip select limit again
eabbc26 
The spi chipselect limit SPI_CS_CNT_MAX was raised with commit
2f8c7c3 ("spi: Raise limit on number of chip selects") from 4 to 16
to accommodate spi controllers with more than 4 chip selects, and then
later to 24 with commit 96893cd ("spi: Raise limit on number of
chip selects to 24").

Now that we removed SPI_CS_CNT_MAX limiting the chip selects of
controllers, we can reduce the amount of chip selects per device again
to 4, the original value.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-7-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@KanjiMonster @machschmitt
spi: rename SPI_CS_CNT_MAX => SPI_DEVICE_CS_CNT_MAX
f87c1de 
Rename SPI_CS_CNT_MAX to SPI_DEVICE_CS_CNT_MAX to make it more obvious
that this is the max number of CS per device supported, not per
controller.

[marcelo.schmitt@analog.com: dropped rename on spi-cadence-quadspi.c]
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-8-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@dlech @machschmitt
include: adi-axi-common: add version check function
c2f81a1 
Add a version check function for checking ADI AXI IP core versions.

These cores use a semantic versioning scheme, so it is useful to have
a version check function that can check the minor version to enable
features in driver while maintaining backward compatibility.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Link: https://patch.msgid.link/20250815-spi-axi-spi-enigne-improve-version-checks-v1-1-13bde357d5b6@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@dlech @machschmitt
spi: axi-spi-engine: use adi_axi_pcore_ver_gteq()
2ea5cad 
Make use of the adi_axi_pcore_ver_gteq() helper to make version checks
more readable and robust against a major version bump.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Link: https://patch.msgid.link/20250815-spi-axi-spi-enigne-improve-version-checks-v1-2-13bde357d5b6@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@dlech @machschmitt
spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays
df5e6aa 
Change spi-rx-bus-width and spi-tx-bus-width properties from single
uint32 values to arrays of uint32 values. This allows describing SPI
peripherals connected to controllers that have multiple data lanes for
receiving or transmitting two or more words in parallel.

Each index in the array corresponds to a physical data lane (one or more
wires depending on the bus width). Additional mapping properties will be
needed in cases where a lane on the controller or peripheral is skipped.

Bindings that make use of this property are updated in the same commit
to avoid validation errors.

The adi,ad4030 binding can now better describe the chips multi-lane
capabilities, so that binding is refined and gets a new example.

Converting from single uint32 to array of uint32 does not break .dts/
.dtb files since there is no difference between specifying a single
uint32 value and an array with a single uint32 value in devicetree.

[marcelo.schmitt@analog.com: dropped andestech,ae350-spi.yaml update]
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-1-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@dlech @machschmitt
spi: dt-bindings: add spi-{tx,rx}-lane-map properties
fdb67f1 
Add spi-tx-lane-map and spi-rx-lane-map properties to the SPI peripheral
device tree binding. These properties allow specifying the mapping of
peripheral data lanes to controller data lanes. This is needed e.g. when
some lanes are skipped on the controller side so that the controller
can correctly route data to/from the peripheral.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-2-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@dlech @machschmitt
spi: support controllers with multiple data lanes
f5477cf 
Add support for SPI controllers with multiple physical SPI data lanes.
(A data lane in this context means lines connected to a serializer, so a
controller with two data lanes would have two serializers in a single
controller).

This is common in the type of controller that can be used with parallel
flash memories, but can be used for general purpose SPI as well.

To indicate support, a controller just needs to set ctlr->num_data_lanes
to something greater than 1. Peripherals indicate which lane they are
connected to via device tree (ACPI support can be added if needed).

The spi-{tx,rx}-bus-width DT properties can now be arrays. The length of
the array indicates the number of data lanes, and each element indicates
the bus width of that lane. For now, we restrict all lanes to have the
same bus width to keep things simple. Support for an optional controller
lane mapping property is also implemented.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-3-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@dlech @machschmitt
spi: add multi_lane_mode field to struct spi_transfer
d5b850b 
Add a new multi_lane_mode field to struct spi_transfer to allow
peripherals that support multiple SPI lanes to be used with a single
SPI controller.

This requires both the peripheral and the controller to have multiple
serializers connected to separate data lanes. It could also be used with
a single controller and multiple peripherals that are functioning as a
single logical device (similar to parallel memories).

Acked-by: Nuno Sá <nuno.sa@analog.com>
Acked-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-4-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@dlech @machschmitt
spi: Documentation: add page on multi-lane support
3e58650 
Add a new page to Documentation/spi/ describing how multi-lane SPI
support works. This is uncommon functionality so it deserves its own
documentation page.

Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-5-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@dlech @machschmitt
spi: dt-bindings: adi,axi-spi-engine: add multi-lane support
4f22589 
Extend the ADI AXI SPI engine binding for multiple data lanes. This SPI
controller has a capability to read multiple data words at the same
time (e.g. for use with simultaneous sampling ADCs). The current FPGA
implementation can support up to 8 data lanes at a time (depending on a
compile-time configuration option).

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-6-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@dlech @machschmitt
spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE
c64b612 
Add support for SPI_MULTI_LANE_MODE_STRIPE to the AXI SPI engine driver.

The v2.0.0 version of the AXI SPI Engine IP core supports multiple
lanes. This can be used with SPI_MULTI_LANE_MODE_STRIPE to support
reading from simultaneous sampling ADCs that have a separate SDO line
for each analog channel. This allows reading all channels at the same
time to increase throughput.

Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-7-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@nunojsa
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nunojsa commented Mar 2, 2026

W have some commits in here that are on other PRs. Seems like we need to merge those first. Also, is all of this absolutely necessary? This will bring me some pain next time I need to merge the spi subystem

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@machschmitt @nunojsa @Skallwar @robherring @andy-shev @KanjiMonster @marckleinebudde @dlech