MT6589 DRM and Blade panels

[akku1139]

thanks to rva3
https://github.com/mt6572-mainline/linux

[akku1139]

maybe needed

mt6572-mainline@0b7a932
mt6572-mainline@b768977

[akku1139]

TODO:

mmsys (done by claude)
mt6572-mainline@7278659

mutex (done)
mt6572-mainline@a0b799a

ovl (done)
mt6572-mainline@39086e4

dsi (done)
mt6572-mainline@af8df08

drm main (done with mt2701_mmsys_driver_data)
mt6572-mainline@4fe7dec

[akku1139]

mmsys routing: ddp_path.c

[akku1139]

m4u hacking

#define M4U_BASE0                0xf0205200
#define M4U_BASE1                0xf0205800 //0x16010000
#define M4U_BASEg                0xf0205000

/* =============================	==================================
 * 					  M4U global        	
 * =============================	================================== */
#define REG_MMUg_CTRL           	 (0x0+M4U_BASEg)
 #define F_MMUg_CTRL_INV_EN0    	 (1<<0)
 #define F_MMUg_CTRL_INV_EN1    	 (1<<1)
 #define F_MMUg_CTRL_INV_EN2    	 (1<<2)
 #define F_MMUg_CTRL_PRE_LOCK(en)    F_BIT_VAL(en, 3)
 #define F_MMUg_CTRL_PRE_EN     	 (1<<4)
                                	
#define REG_MMUg_INVLD          	 (0x4  + M4U_BASEg)    
 #define F_MMUg_INV_ALL         	 0x2   
 #define F_MMUg_INV_RANGE       	 0x1   
                                	    
#define REG_MMUg_INVLD_SA        	 (0x8  + M4U_BASEg)     
#define REG_MMUg_INVLD_EA          (0xC  + M4U_BASEg)    
#define REG_MMUg_PT_BASE           (0x10 + M4U_BASEg)
 #define F_MMUg_PT_VA_MSK        0xffff0000


#define REG_MMUg_L2_SEL            (0x18 + M4U_BASEg)
    #define F_MMUg_L2_SEL_FLUSH_EN(en)          F_BIT_VAL(en, 3)
    #define F_MMUg_L2_SEL_L2_ULTRA(en)          F_BIT_VAL(en, 2)
    #define F_MMUg_L2_SEL_L2_SHARE(en)          F_BIT_VAL(en, 1)
    #define F_MMUg_L2_SEL_L2_BUS_SEL(go_emi)    F_BIT_VAL(go_emi, 0)


    
#define REG_MMUg_DCM               (0x1C + M4U_BASEg)
    #define F_MMUg_DCM_ON(on)       F_BIT_VAL(on, 0)


//registers for security
#define REG_MMUg_CTRL_SEC          (0x20 + M4U_BASEg)
 #define F_MMUg_CTRL_SEC_INV_EN0     (1<<0)
 #define F_MMUg_CTRL_SEC_INV_EN1     (1<<1)
 #define F_MMUg_CTRL_SEC_INV_EN2     (1<<2)
 #define F_MMUg_CTRL_SEC_PRE_LOCK    (1<<3)
 #define F_MMUg_CTRL_SEC_PRE_EN      (1<<4)
 #define F_MMUg_CTRL_SEC_DBG         (1<<5)


#define REG_MMUg_INVLD_SEC           (0x24+M4U_BASEg)
 #define F_MMUg_INV_SEC_ALL          0x2 
 #define F_MMUg_INV_SEC_RANGE        0x1 
                                     
#define REG_MMUg_INVLD_SA_SEC        (0x28+M4U_BASEg)	    
#define REG_MMUg_INVLD_EA_SEC        (0x2C+M4U_BASEg)
#define REG_MMUg_PT_BASE_SEC         (0x30+M4U_BASEg)
 #define F_MMUg_PT_VA_MSK_SEC        0xffff0000




#define REG_MMUg_SEC_ABORT_INFO      (0x34+M4U_BASEg)
    
                                                                          
#define REG_MMUg_INFA_CTRL           (0x80+M4U_BASEg)
#define REG_MMUg_INFA_ST1            (0x84+M4U_BASEg)
#define REG_MMUg_INFA_ST2            (0x88+M4U_BASEg)
#define REG_MMUg_INFA_ST3            (0x8c+M4U_BASEg)

https://github.com/bq/aquaris-5/blob/bc1d0d0e35c969670e2d869001be944ad0c9c5e5/mediatek/platform/mt6589/kernel/drivers/m4u/m4u_reg.h#L365-L419

mt6572

/* =============================	==================================
 * 					  M4U global        	
 * =============================	================================== */
#define REG_MMUg_CTRL           	 (0x5D8  + M4U_BASE)
 #define F_MMUg_CTRL_INV_EN0    	 (1<<0)
                                	
#define REG_MMUg_INVLD          	 (0x5C0  + M4U_BASE)    
 #define F_MMUg_INV_ALL         	 0x2   
 #define F_MMUg_INV_RANGE       	 0x1   
                                	    
#define REG_MMUg_INVLD_SA        	 (0x5C4  + M4U_BASE)     
#define REG_MMUg_INVLD_EA            (0x5C8  + M4U_BASE)    
#define REG_MMUg_PT_BASE             (0x0    + M4U_BASE)
 #define F_MMUg_PT_VA_MSK        0xffff0000 //64kB alignment
    
#define REG_MMUg_DCM               (0x5F0 + M4U_BASEg)
    #define F_MMUg_DCM_ON(on)       F_BIT_VAL(on, 0)


//registers for security
#define REG_MMUg_CTRL_SEC          (0x5DC + M4U_BASE)
 #define F_MMUg_CTRL_SEC_INV_EN0     (1<<0)
 #define F_MMUg_CTRL_SEC_INV_EN0_MSK (1)
 #define F_MMUg_CTRL_SEC_DBG         (1<<5)
 #define F_SEC_INT_EN                (1<<12)


#define REG_MMUg_INVLD_SEC           (0x5CC+M4U_BASE)
 #define F_MMUg_INV_SEC_RANGE        0x1 
                                     
#define REG_MMUg_PT_BASE_SEC         (0x4 +M4U_BASE)
 #define F_MMUg_PT_VA_MSK_SEC        0xffff0000 //64kB alignment

https://github.com/LIFECorp/mediatek/blob/1f49d8c87b839651bc89afc870277e8e0f2e2d55/platform/mt6572/kernel/drivers/m4u/m4u_reg.h#L292-L322

#define REG_MMU_FAULT_ST			0x224
#define REG_MMU_FAULT_VA			0x228
#define REG_MMU_INVLD_PA			0x22C
#define REG_MMU_INT_ID				0x388
#define REG_MMU_INVALIDATE			0x5c0
#define REG_MMU_INVLD_START_A			0x5c4
#define REG_MMU_INVLD_END_A			0x5c8

linux/drivers/iommu/mtk_iommu_v1.c

Lines 70 to 76 in 84cb16e

	#define REG_MMU_FAULT_ST 0x224
	#define REG_MMU_FAULT_VA 0x228
	#define REG_MMU_INVLD_PA 0x22C
	#define REG_MMU_INT_ID 0x388
	#define REG_MMU_INVALIDATE 0x5c0
	#define REG_MMU_INVLD_START_A 0x5c4
	#define REG_MMU_INVLD_END_A 0x5c8

[akku1139]

shared-dma-pool

[akku1139]

0x10205000 : M4U_CTRL
0x10205410 : MMU_CTRL_REG

[akku1139]

sleep 15
mount -t debugfs none /sys/kernel/debug
echo "clocksource:"
cat /sys/devices/system/clocksource/clocksource0/current_clocksource
echo "available_clocksource:"
cat /sys/devices/system/clocksource/clocksource0/available_clocksource
echo "block devices:"
ls /sys/class/block/
echo "not proved drivers:"
find /sys/bus/platform/devices/ -maxdepth 1 -mindepth 1 \
    '!' -exec test -e "{}/driver" ';' -print | xargs -I {} basename {}
echo "dmesg part:"
dmesg | grep -i "probe failed"
dmesg | grep -i "err"
dmesg | grep -i "unable"
dmesg | grep -i "cannot"
dmesg | grep -i "can't"
dmesg | grep -i "fail"
dmesg | grep -i "waiting on"
#dmesg | grep "mtk-power-controller"
echo "devices_deferred:"
cat /sys/kernel/debug/devices_deferred
echo "pm_genpd_summary:"
cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
ls -l /sys/bus/platform/devices/10205200.iommu/supplier:*
ls -l /sys/bus/platform/devices/14003000.ovl/supplier:*
ls -l /sys/bus/platform/devices/14011000.mutex/supplier:*

while true
do
sleep 15
done

[akku1139]

smi_ao_base

[akku1139]

#define REG_SMI_SECUR_CON(x)       	  (0x05C0+SMI_COMMON_AO_BASE+((x)<<2))
#define REG_SMI_SECUR_CON_OF_PORT(port)     REG_SMI_SECUR_CON(((m4u_port_2_smi_port(port))>>3))
    #define F_SMI_SECUR_CON_SECURE(port)        ((1)<<(((m4u_port_2_smi_port(port))&0x7)<<2))
    #define F_SMI_SECUR_CON_DOMAIN(port, val)   (((val)&0x3)<<((((m4u_port_2_smi_port(port))&0x7)<<2)+1))
    #define F_SMI_SECUR_CON_VIRTUAL(port)       ((1)<<((((m4u_port_2_smi_port(port))&0x7)<<2)+3))
    #define F_SMI_SECUR_CON_MASK(port)          ((0xf)<<((((m4u_port_2_smi_port(port))&0x7)<<2)))

https://github.com/bq/aquaris-5/blob/bc1d0d0e35c969670e2d869001be944ad0c9c5e5/mediatek/platform/mt6589/kernel/drivers/m4u/m4u_reg.h#L338-L343

[akku1139]

/* Below are about mmu enable registers, they are different in SoCs */
/* gen1: mt2701 */
#define REG_SMI_SECUR_CON_BASE		0x5c0


/* every register control 8 port, register offset 0x4 */
#define REG_SMI_SECUR_CON_OFFSET(id)	(((id) >> 3) << 2)
#define REG_SMI_SECUR_CON_ADDR(id)	\
	(REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))

linux/drivers/memory/mtk-smi.c

Lines 65 to 72 in 6316de5

	/* Below are about mmu enable registers, they are different in SoCs */
	/* gen1: mt2701 */
	#define REG_SMI_SECUR_CON_BASE 0x5c0
	/* every register control 8 port, register offset 0x4 */
	#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
	#define REG_SMI_SECUR_CON_ADDR(id) \
	(REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))