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Merged
arghunter merged 8 commits into from
Apr 5, 2026
Merged

Multiplication Extension Fully working and tested with mandelbrot #5

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6100af3
basic alu
arghunter Mar 24, 2026
f15074e
alu integrated
arghunter Mar 24, 2026
82140e9
comp error fixes
arghunter Mar 24, 2026
b89d589
mult implemented
arghunter Mar 24, 2026
eb2c02d
git push
arghunter Apr 5, 2026
11e91c8
m completed will test
arghunter Apr 5, 2026
a579ace
seems to work
arghunter Apr 5, 2026
f0d2b70
it works
arghunter Apr 5, 2026
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2 changes: 1 addition & 1 deletion RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
// clk_out2__200.00000______0.000______50.0______114.829_____98.575
// clk_out2__25.00000______0.000______50.0______175.402_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand Down
2 changes: 1 addition & 1 deletion RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
// clk_out2__200.00000______0.000______50.0______114.829_____98.575
// clk_out2__25.00000______0.000______50.0______175.402_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand Down
56 changes: 28 additions & 28 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml
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Expand Up @@ -1314,11 +1314,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
<spirit:value>Sun Apr 05 17:27:05 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7df132ee</spirit:value>
<spirit:value>9:ad4d551b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1333,11 +1333,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
<spirit:value>Sun Apr 05 17:27:05 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7df132ee</spirit:value>
<spirit:value>9:ad4d551b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1352,11 +1352,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
<spirit:value>Sun Apr 05 17:27:05 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e49cf90</spirit:value>
<spirit:value>9:067c9c1a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1371,11 +1371,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
<spirit:value>Sun Apr 05 17:27:05 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e49cf90</spirit:value>
<spirit:value>9:067c9c1a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1386,7 +1386,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e49cf90</spirit:value>
<spirit:value>9:067c9c1a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1397,7 +1397,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ea0c8e5a</spirit:value>
<spirit:value>9:7443706c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1411,11 +1411,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
<spirit:value>Sun Apr 05 17:27:05 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:0455ee43</spirit:value>
<spirit:value>9:4527b5ca</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1429,11 +1429,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
<spirit:value>Sun Apr 05 17:27:05 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e49cf90</spirit:value>
<spirit:value>9:067c9c1a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1444,7 +1444,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e49cf90</spirit:value>
<spirit:value>9:067c9c1a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1460,11 +1460,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
<spirit:value>Sun Apr 05 17:27:05 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e49cf90</spirit:value>
<spirit:value>9:067c9c1a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1478,11 +1478,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
<spirit:value>Sun Apr 05 17:27:05 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e49cf90</spirit:value>
<spirit:value>9:067c9c1a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand Down Expand Up @@ -2725,7 +2725,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_OUTCLK_SUM_ROW2</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">clk_out2__200.00000______0.000______50.0______114.829_____98.575</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">clk_out2__25.00000______0.000______50.0______175.402_____98.575</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_OUTCLK_SUM_ROW3</spirit:name>
Expand Down Expand Up @@ -2753,7 +2753,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="255">200.000</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="255">25</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
Expand Down Expand Up @@ -2837,7 +2837,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT2_OUT_FREQ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">200.00000</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">25.00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT3_OUT_FREQ</spirit:name>
Expand Down Expand Up @@ -3005,7 +3005,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT1_DIVIDE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">5</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">40</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT2_DIVIDE</spirit:name>
Expand Down Expand Up @@ -3531,7 +3531,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_DIVIDE2_AUTO</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE2_AUTO" spirit:order="411">0.125</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE2_AUTO" spirit:order="411">1.0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_DIVIDE3_AUTO</spirit:name>
Expand Down Expand Up @@ -3639,7 +3639,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT1_ACTUAL_FREQ</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ" spirit:order="712">200.00000</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ" spirit:order="712">25.00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT2_ACTUAL_FREQ</spirit:name>
Expand Down Expand Up @@ -4352,7 +4352,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="65" spirit:configGroups="0 NoDisplay">200.000</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="65" spirit:configGroups="0 NoDisplay">25</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLKOUT2_REQUESTED_PHASE</spirit:name>
Expand Down Expand Up @@ -4688,7 +4688,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT1_DIVIDE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay">5</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay">40</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
Expand Down Expand Up @@ -4997,7 +4997,7 @@
<spirit:parameter>
<spirit:name>CLKOUT2_JITTER</spirit:name>
<spirit:displayName>Clkout2 Jitter</spirit:displayName>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_JITTER" spirit:order="1002">114.829</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_JITTER" spirit:order="1002">175.402</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLKOUT2_PHASE_ERROR</spirit:name>
Expand Down
4 changes: 2 additions & 2 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
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Expand Up @@ -54,7 +54,7 @@
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
// clk_out2__200.00000______0.000______50.0______114.829_____98.575
// clk_out2__25.00000______0.000______50.0______175.402_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand Down Expand Up @@ -134,7 +134,7 @@ wire clk_in2_clk_wiz_0;
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (5),
.CLKOUT1_DIVIDE (40),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
Expand Down
4 changes: 2 additions & 2 deletions ...Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
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Expand Up @@ -2,7 +2,7 @@
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
// Date : Fri Mar 13 02:38:01 2026
// Date : Sun Apr 5 13:21:14 2026
// Host : arya running 64-bit EndeavourOS Linux
// Command : write_verilog -force -mode funcsim -rename_top clk_wiz_0 -prefix
// clk_wiz_0_ clk_wiz_0_sim_netlist.v
Expand Down Expand Up @@ -111,7 +111,7 @@ module clk_wiz_0_clk_wiz_0_clk_wiz
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(5),
.CLKOUT1_DIVIDE(40),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
Expand Down
4 changes: 2 additions & 2 deletions ...ffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
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Expand Up @@ -2,7 +2,7 @@
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
-- Date : Fri Mar 13 02:38:01 2026
-- Date : Sun Apr 5 13:21:14 2026
-- Host : arya running 64-bit EndeavourOS Linux
-- Command : write_vhdl -force -mode funcsim -rename_top clk_wiz_0 -prefix
-- clk_wiz_0_ clk_wiz_0_sim_netlist.vhdl
Expand Down Expand Up @@ -94,7 +94,7 @@ mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 5,
CLKOUT1_DIVIDE => 40,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
Expand Down
2 changes: 1 addition & 1 deletion RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
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Expand Up @@ -2,7 +2,7 @@
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
// Date : Fri Mar 13 02:38:01 2026
// Date : Sun Apr 5 13:21:14 2026
// Host : arya running 64-bit EndeavourOS Linux
// Command : write_verilog -force -mode synth_stub -rename_top clk_wiz_0 -prefix
// clk_wiz_0_ clk_wiz_0_stub.v
Expand Down
2 changes: 1 addition & 1 deletion RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
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Expand Up @@ -2,7 +2,7 @@
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
-- Date : Fri Mar 13 02:38:01 2026
-- Date : Sun Apr 5 13:21:14 2026
-- Host : arya running 64-bit EndeavourOS Linux
-- Command : write_vhdl -force -mode synth_stub -rename_top clk_wiz_0 -prefix
-- clk_wiz_0_ clk_wiz_0_stub.vhdl
Expand Down
2 changes: 1 addition & 1 deletion RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo
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Expand Up @@ -53,7 +53,7 @@
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
// clk_out2__200.00000______0.000______50.0______114.829_____98.575
// clk_out2__25.00000______0.000______50.0______175.402_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand Down
2 changes: 1 addition & 1 deletion ...old-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt
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Expand Up @@ -5,7 +5,7 @@
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026
# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026
#
################################################################################

Expand Down
2 changes: 1 addition & 1 deletion ...d-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh
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Expand Up @@ -2,7 +2,7 @@
#**********************************************************************************************************
# Vivado (TM) v2025.2 (64-bit)
#
# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026
# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Expand Down
2 changes: 1 addition & 1 deletion ...ffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt
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Expand Up @@ -5,7 +5,7 @@
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026
# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026
#
################################################################################

Expand Down
2 changes: 1 addition & 1 deletion ...old-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh
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Expand Up @@ -2,7 +2,7 @@
#**********************************************************************************************************
# Vivado (TM) v2025.2 (64-bit)
#
# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026
# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Expand Down
2 changes: 1 addition & 1 deletion ...fold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt
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Expand Up @@ -5,7 +5,7 @@
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026
# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026
#
################################################################################

Expand Down
2 changes: 1 addition & 1 deletion ...ld-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh
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Expand Up @@ -2,7 +2,7 @@
#**********************************************************************************************************
# Vivado (TM) v2025.2 (64-bit)
#
# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026
# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Expand Down
2 changes: 1 addition & 1 deletion ...Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt
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Expand Up @@ -5,7 +5,7 @@
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026
# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026
#
################################################################################

Expand Down
2 changes: 1 addition & 1 deletion ...affold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh
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Expand Up @@ -2,7 +2,7 @@
#**********************************************************************************************************
# Vivado (TM) v2025.2 (64-bit)
#
# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026
# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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2 changes: 1 addition & 1 deletion ...fold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt
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# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026
# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026
#
################################################################################

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