💫
Checkmate
Electronic's and Communication Engineer
Popular repositories Loading
-
RISC-V_CPU
RISC-V_CPU PublicA custom 32-bit RISC processor implemented in Verilog, demonstrating datapath, control logic, and instruction execution.
-
Single_Cycle_RISC-V
Single_Cycle_RISC-V PublicThis project implements a RISC-V Single-Cycle processor in Verilog, integrating PC, ALU, register file, control, and memory into a simple reference CPU design.
-
UART_TX-RX
UART_TX-RX PublicA Verilog-based full-duplex UART transmitter and receiver with configurable baud rate and serial-to-parallel data conversion.
-
Asynchronous-FIFO
Asynchronous-FIFO PublicA Verilog asynchronous FIFO using Gray-coded pointers for safe clock domain crossing and reliable full/empty detection.
Verilog 2
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.

