GICR Enumeration Issue

[ForeverYolo]

Currently, Hvisor enumerates GICR sequentially for MAX_CPU_NUM times.
Therefore, Hvisor actually assumes that the GICR regions of each CPU are arranged consecutively within the GICR.
In fact, this assumption is not valid. In the Nvidia Orin Nano development board, the GICR regions of the first 4 CPUs are contiguous, while the GICR regions of the latter 2 CPUs are separated from the former.
The current hvisor will not be able to handle this situation; it will only enumerate the GICR regions of the first four CPUs, causing the last two CPUs to fail to start because no GICR regions are found. This needs to be addressed.

[ForeverYolo]

[ForeverYolo]

The above image shows the output after a simple modification of hvisor, and it can be seen that the GICR regions of the first four CPUs and the last two CPUs are indeed not continuous.