Modify JTAG settings for different boards

[LeonardooAlves]

Hi, I hope you are well.

I am trying to deploy the Flute on a Zynq UltraScale+ ZCU102 board. I noticed on the Makefile that the JTAG is built based on the XCVU9P board. Hence, I modified the JtagTap.bsv to include my board specifications:

`elsif XILINX_XCZU9EG
typedef 12 IR_LENGTH;

`elsif XILINX_XCZU9EG

Bit#(IR_LENGTH) ir_dtmcs = 'b100100100010;    // USER3
                        // 'b100100000010;    USER1

Bit#(IR_LENGTH) ir_dmi = 'b100100000011; // USER 2
`endif

I am wondering if I need to do any other modification in order to correctly generate the Jtag Verilog files to be used with OpenOCD.

Thank you.