From 6100af357983be32fb014d417392281aec610c12 Mon Sep 17 00:00:00 2001 From: ag Date: Tue, 24 Mar 2026 03:48:06 -0400 Subject: [PATCH 1/8] basic alu --- src/main/scala/RISCV/ALU.scala | 91 ++++++++++++++------------------- src/main/scala/RISCV/Main.scala | 24 ++++----- 2 files changed, 48 insertions(+), 67 deletions(-) diff --git a/src/main/scala/RISCV/ALU.scala b/src/main/scala/RISCV/ALU.scala index 8ee4a17..efb3261 100644 --- a/src/main/scala/RISCV/ALU.scala +++ b/src/main/scala/RISCV/ALU.scala @@ -4,71 +4,54 @@ import chisel3._ import chisel3.util._ import _root_.circt.stage.ChiselStage -/** @param width - * Bit width (default: 32 bits) - * - * The Arithmetic Logic Unit (ALU) for RISC-V Supports: Addition, Multiplication, Comparison, Bitwise operations - * - * I/O: operation: 4-bit operation code signed: boolean to indicate if operands are signed (Only used for comparisons) a: first operand b: - * second operand output: result of the operation - * - * Operation Codes: 0000: Addition 0001: Multiplication 0010: Comparison (outputs 3 bits: gt, eq, lt) 0011: Bitwise AND 0100: Bitwise OR - * 0101: Bitwise XOR 0110: Bitwise NOT (outputs NOT a) 0111: Logical shift left 1000: Logical shift right 1001: Arithmetic shift right - */ + class ALU(val width: Int = 32) extends Module { val io = IO(new Bundle { - val operation = Input(UInt(4.W)); // 4-bit operation code - val signed = Input(Bool()); // Treat operands as signed if true + val func7 = Input(UInt(7.W)); + val func3 = Input(UInt(3.W)); val a = Input(UInt(width.W)); // First operand val b = Input(UInt(width.W)); // Second operand val output = Output(UInt(width.W)); // Result of the operation }) io.output := 0.U; - - switch(io.operation) { - is("b0000".U) { - io.output := io.a + io.b; // Addition - } - is("b0001".U) { - io.output := io.a * io.b; // Multiplication - } - is("b0010".U) { - when(io.signed) { - val a_s = io.a.asSInt - val b_s = io.b.asSInt - val gt_s = a_s > b_s - val eq_s = a_s === b_s - val lt_s = a_s < b_s - io.output := Cat(0.U((width - 3).W), gt_s, eq_s, lt_s); + switch(io.func3){ + is("b000".U){ + io.output := io.a + io.b + } + //SLLI + is("b001".U){ + io.output := io.a << io.b(4,0) + } + //SLTI + is("b010".U){ + io.output := Mux(io.a.asSInt < io.b.asSInt, 1.U, 0.U) + } + //SLTIU + is("b011".U){ + io.output := Mux(io.a < io.b, 1.U, 0.U) + } + //XOR + is("b100".U){ + io.output := io.a ^ io.b; + } + //SRAI, SRLI + is("b101".U) { + when(io.func7(5)) { + io.output := (io.a.asSInt >> io.b(4, 0)).asUInt }.otherwise { - val gt = io.a > io.b; // Comparison - val eq = io.a === io.b; - val lt = io.a < io.b; - - io.output := Cat(0.U((width - 3).W), gt, eq, lt); + io.output := io.a >> io.b(4, 0) } } - is("b0011".U) { - io.output := io.a & io.b; // Bitwise AND - } - is("b0100".U) { - io.output := io.a | io.b; // Bitwise OR + // OR + is("b110".U) { + io.output := io.a | io.b } - is("b0101".U) { - io.output := io.a ^ io.b; // Bitwise XOR - } - is("b0110".U) { - io.output := ~io.a; // Bitwise NOT - } - is("b0111".U) { - io.output := io.a << io.b(4, 0); // Logical shift left - } - is("b1000".U) { - io.output := io.a >> io.b(4, 0); // Logical shift right - } - is("b1001".U) { - io.output := (io.a.asSInt >> io.b(4, 0)).asUInt // Arithmetic shift right + //AND + is("b111".U) { + io.output := io.a & io.b } + } -} + + } diff --git a/src/main/scala/RISCV/Main.scala b/src/main/scala/RISCV/Main.scala index f9799c4..61a7e80 100644 --- a/src/main/scala/RISCV/Main.scala +++ b/src/main/scala/RISCV/Main.scala @@ -40,11 +40,11 @@ class Main() extends Module { registers.io.read_address_c := 0.U(5.W) registers.io.in := 0.U(32.W) - val alu = Module(new ALU()) - alu.io.operation := 0.U(3.W) - alu.io.signed := false.B - alu.io.a := 0.U(32.W) - alu.io.b := 0.U(32.W) + // val alu = Module(new ALU()) + // alu.io.operation := 0.U(3.W) + // alu.io.signed := false.B + // alu.io.a := 0.U(32.W) + // alu.io.b := 0.U(32.W) val memory = Module(new Memory()) memory.io.btns := io.btns @@ -179,16 +179,14 @@ class Main() extends Module { registers.io.write_enable := true.B program_pointer := pc_plus_4 stage := 0.U - - val alu_b = Mux(opcode_buffer === "b0010011".U, immediate_buffer, out_b_buffer) - + val neg = Mux(opcode_buffer === "b0110011".U && funct7_buffer(5), - out_b_buffer, out_b_buffer) + val alu_b = Mux(opcode_buffer === "b0010011".U, immediate_buffer, neg) + switch(funct3_buffer){ is("b000".U){ - when(opcode_buffer === "b0110011".U && funct7_buffer(5)) { - registers.io.in := out_a_buffer - alu_b - }.otherwise { - registers.io.in := out_a_buffer + alu_b - } + + registers.io.in := out_a_buffer + alu_b + } //SLLI is("b001".U){ From f15074eb704ddc03ad69b06baa19021b1ab7383d Mon Sep 17 00:00:00 2001 From: ag Date: Tue, 24 Mar 2026 12:13:28 -0400 Subject: [PATCH 2/8] alu integrated --- src/main/scala/RISCV/Main.scala | 55 ++++++--------------------------- 1 file changed, 9 insertions(+), 46 deletions(-) diff --git a/src/main/scala/RISCV/Main.scala b/src/main/scala/RISCV/Main.scala index 61a7e80..7d45955 100644 --- a/src/main/scala/RISCV/Main.scala +++ b/src/main/scala/RISCV/Main.scala @@ -40,11 +40,7 @@ class Main() extends Module { registers.io.read_address_c := 0.U(5.W) registers.io.in := 0.U(32.W) - // val alu = Module(new ALU()) - // alu.io.operation := 0.U(3.W) - // alu.io.signed := false.B - // alu.io.a := 0.U(32.W) - // alu.io.b := 0.U(32.W) + val memory = Module(new Memory()) memory.io.btns := io.btns @@ -98,6 +94,12 @@ class Main() extends Module { io.debug_1 := program_pointer io.debug_2 := stage ## opcode_buffer + val alu = Module(new ALU()) + alu.io.func7 = funct7_buffer; + alu.io.func3 := funct3_buffer; + alu.io.a := out_a_buffer; + alu.io.b := 0.U(32.W) + when(io.execute) { printf("\n"); printf("Stage: %d\n", stage); @@ -181,48 +183,9 @@ class Main() extends Module { stage := 0.U val neg = Mux(opcode_buffer === "b0110011".U && funct7_buffer(5), - out_b_buffer, out_b_buffer) val alu_b = Mux(opcode_buffer === "b0010011".U, immediate_buffer, neg) - - switch(funct3_buffer){ - is("b000".U){ + alu.io.b := alu_b + registers.io.in = alu.io.output - registers.io.in := out_a_buffer + alu_b - - } - //SLLI - is("b001".U){ - registers.io.in := out_a_buffer << alu_b(4,0) - } - //SLTI - is("b010".U){ - registers.io.in := Mux(out_a_buffer.asSInt < alu_b.asSInt, 1.U, 0.U) - } - //SLTIU - is("b011".U){ - registers.io.in := Mux(out_a_buffer < alu_b, 1.U, 0.U) - } - //XOR - is("b100".U){ - registers.io.in := out_a_buffer ^ alu_b; - } - //SRAI, SRLI - is("b101".U) { - when(funct7_buffer(5)) { - registers.io.in := (out_a_buffer.asSInt >> alu_b(4, 0)).asUInt - }.otherwise { - registers.io.in := out_a_buffer >> alu_b(4, 0) - } - } - // OR - is("b110".U) { - registers.io.in := out_a_buffer | alu_b - } - //AND - is("b111".U) { - registers.io.in := out_a_buffer & alu_b - } - - - } } //Branch is("b1100011".U){ From 82140e988d9e3c58b6a64215bf31b28c76193dd9 Mon Sep 17 00:00:00 2001 From: ag Date: Tue, 24 Mar 2026 13:58:42 -0400 Subject: [PATCH 3/8] comp error fixes --- RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr | 15 +++++++++++++++ src/main/scala/RISCV/Main.scala | 4 ++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr index 11d04dd..4a9ee7c 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr @@ -106,6 +106,14 @@ + + + + + + + + @@ -127,6 +135,13 @@ + + + + + + + diff --git a/src/main/scala/RISCV/Main.scala b/src/main/scala/RISCV/Main.scala index 7d45955..5b78f64 100644 --- a/src/main/scala/RISCV/Main.scala +++ b/src/main/scala/RISCV/Main.scala @@ -95,7 +95,7 @@ class Main() extends Module { io.debug_2 := stage ## opcode_buffer val alu = Module(new ALU()) - alu.io.func7 = funct7_buffer; + alu.io.func7 := funct7_buffer; alu.io.func3 := funct3_buffer; alu.io.a := out_a_buffer; alu.io.b := 0.U(32.W) @@ -184,7 +184,7 @@ class Main() extends Module { val neg = Mux(opcode_buffer === "b0110011".U && funct7_buffer(5), - out_b_buffer, out_b_buffer) val alu_b = Mux(opcode_buffer === "b0010011".U, immediate_buffer, neg) alu.io.b := alu_b - registers.io.in = alu.io.output + registers.io.in := alu.io.output } //Branch From b89d589bb9694ffb4620e1b5976f1913981aab5e Mon Sep 17 00:00:00 2001 From: ag Date: Tue, 24 Mar 2026 18:50:18 -0400 Subject: [PATCH 4/8] mult implemented --- src/main/scala/RISCV/ALU.scala | 46 ++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/src/main/scala/RISCV/ALU.scala b/src/main/scala/RISCV/ALU.scala index efb3261..e847eb5 100644 --- a/src/main/scala/RISCV/ALU.scala +++ b/src/main/scala/RISCV/ALU.scala @@ -13,45 +13,71 @@ class ALU(val width: Int = 32) extends Module { val b = Input(UInt(width.W)); // Second operand val output = Output(UInt(width.W)); // Result of the operation }) - io.output := 0.U; + i_alu := 0.U; + i_alu = Wire(UInt(width.W)); + m_alu = Wire(UInt(width.W)); + + + val m_in_a = io.a; + val m_in_b = io.b; + val mult_out = Wire(64.W); + mult_out := m_in_a * m_in_b; + switch(io.func3){ + is("b000".U,"b001".U,"b010".U,"b011".U){ + + val m_in_a = Mux(io.func3(1) && io.func3(0),io.a, io.a.asSInt) + val m_in_b = Mux(io.func3(1) ,io.b, io.b.asSInt) + val mult_out = Wire(64.W) + + mult_out := m_in_a * m_in_b; + m_alu := Mux(io.func3 === "b000".U, mult_out(31,0), mult_out(63,32)) + } + } + switch(io.func3){ is("b000".U){ - io.output := io.a + io.b + i_alu := io.a + io.b + m_alu := mult_out(31,0) + } //SLLI is("b001".U){ - io.output := io.a << io.b(4,0) + i_alu := io.a << io.b(4,0) + m_in_a := io.a.asSInt; + m_in_b := io.a.asSInt; + m_alu := mult_out(63,32) } //SLTI is("b010".U){ - io.output := Mux(io.a.asSInt < io.b.asSInt, 1.U, 0.U) + i_alu := Mux(io.a.asSInt < io.b.asSInt, 1.U, 0.U) } //SLTIU is("b011".U){ - io.output := Mux(io.a < io.b, 1.U, 0.U) + i_alu := Mux(io.a < io.b, 1.U, 0.U) } //XOR is("b100".U){ - io.output := io.a ^ io.b; + i_alu := io.a ^ io.b; } //SRAI, SRLI is("b101".U) { when(io.func7(5)) { - io.output := (io.a.asSInt >> io.b(4, 0)).asUInt + i_alu := (io.a.asSInt >> io.b(4, 0)).asUInt }.otherwise { - io.output := io.a >> io.b(4, 0) + i_alu := io.a >> io.b(4, 0) } } // OR is("b110".U) { - io.output := io.a | io.b + i_alu := io.a | io.b } //AND is("b111".U) { - io.output := io.a & io.b + i_alu := io.a & io.b } } + io.output = Mux(func7(0), m_alu, i_alu); } From eb2c02ddafed704cca6fe3d813d6543f1e982404 Mon Sep 17 00:00:00 2001 From: ag Date: Sun, 5 Apr 2026 01:23:30 -0400 Subject: [PATCH 5/8] git push --- src/main/scala/RISCV/ALU.scala | 84 ++++++++++++++++++++++++++-------- 1 file changed, 65 insertions(+), 19 deletions(-) diff --git a/src/main/scala/RISCV/ALU.scala b/src/main/scala/RISCV/ALU.scala index e847eb5..e3fadc5 100644 --- a/src/main/scala/RISCV/ALU.scala +++ b/src/main/scala/RISCV/ALU.scala @@ -14,39 +14,85 @@ class ALU(val width: Int = 32) extends Module { val output = Output(UInt(width.W)); // Result of the operation }) io.output := 0.U; + val i_alu = Wire(UInt(width.W)); + val m_alu = Wire(UInt(width.W)); i_alu := 0.U; - i_alu = Wire(UInt(width.W)); - m_alu = Wire(UInt(width.W)); + m_alu := 0.U + + + - val m_in_a = io.a; - val m_in_b = io.b; - val mult_out = Wire(64.W); - mult_out := m_in_a * m_in_b; - switch(io.func3){ - is("b000".U,"b001".U,"b010".U,"b011".U){ - - val m_in_a = Mux(io.func3(1) && io.func3(0),io.a, io.a.asSInt) - val m_in_b = Mux(io.func3(1) ,io.b, io.b.asSInt) - val mult_out = Wire(64.W) - mult_out := m_in_a * m_in_b; - m_alu := Mux(io.func3 === "b000".U, mult_out(31,0), mult_out(63,32)) + val a_s = io.a.asSInt + val b_s = io.b.asSInt + + switch(io.func3) { + //MUL + is("b000".U) { + m_alu := (a_s * b_s).asUInt(31, 0) + } + //MULH + is("b001".U) { + m_alu := (a_s * b_s).asUInt(63, 32) + } + //MULHSU + is("b010".U) { + val a_ext = Cat(io.a(31), io.a).asSInt + val b_ext = Cat(0.U(1.W), io.b).asSInt + m_alu := (a_ext * b_ext).asUInt(63, 32) + } + //MULHU + is("b011".U) { + m_alu := (io.a * io.b)(63, 32) + } + //DIV + is("b100".U) { + when(io.b === 0.U) { + m_alu := Fill(width, 1.U) + }.elsewhen(io.a === (1.U << (width-1)) && b_s === (-1).S) { + m_alu := io.a + }.otherwise { + m_alu := (a_s / b_s).asUInt + } + } + //DIVU + is("b101".U) { + when(io.b === 0.U) { + m_alu := Fill(width, 1.U) + }.otherwise { + m_alu := io.a / io.b + } + } + //REM + is("b110".U) { + when(io.b === 0.U) { + m_alu := io.a + }.elsewhen(io.a === (1.U << (width-1)) && b_s === (-1).S){ + m_alu := 0.U + }.otherwise { + m_alu := (a_s % b_s).asUInt + } + } + //REMU + is("b111".U) { + when(io.b === 0.U) { + m_alu := io.a + }.otherwise { + m_alu := io.a % io.b + } } } switch(io.func3){ is("b000".U){ i_alu := io.a + io.b - m_alu := mult_out(31,0) } //SLLI is("b001".U){ i_alu := io.a << io.b(4,0) - m_in_a := io.a.asSInt; - m_in_b := io.a.asSInt; - m_alu := mult_out(63,32) + } //SLTI is("b010".U){ @@ -78,6 +124,6 @@ class ALU(val width: Int = 32) extends Module { } } - io.output = Mux(func7(0), m_alu, i_alu); + io.output := Mux(io.func7(0), m_alu, i_alu) } From 11e91c86d6beadfe135e791b3b42c8eed43797ac Mon Sep 17 00:00:00 2001 From: ag Date: Sun, 5 Apr 2026 01:24:09 -0400 Subject: [PATCH 6/8] m completed will test --- src/main/scala/RISCV/ALU.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/RISCV/ALU.scala b/src/main/scala/RISCV/ALU.scala index e3fadc5..0f9b191 100644 --- a/src/main/scala/RISCV/ALU.scala +++ b/src/main/scala/RISCV/ALU.scala @@ -41,7 +41,7 @@ class ALU(val width: Int = 32) extends Module { val a_ext = Cat(io.a(31), io.a).asSInt val b_ext = Cat(0.U(1.W), io.b).asSInt m_alu := (a_ext * b_ext).asUInt(63, 32) - } + } //MULHU is("b011".U) { m_alu := (io.a * io.b)(63, 32) From a579acebd291e7ee0bdf5405c235a20d30ea2822 Mon Sep 17 00:00:00 2001 From: ag Date: Sun, 5 Apr 2026 13:28:39 -0400 Subject: [PATCH 7/8] seems to work --- .../sources_1/ip/clk_wiz_0/clk_wiz_0.v | 2 +- .../sources_1/ip/clk_wiz_0/clk_wiz_0.veo | 2 +- .../sources_1/ip/clk_wiz_0/clk_wiz_0.xml | 56 +++++++++---------- .../ip/clk_wiz_0/clk_wiz_0_clk_wiz.v | 4 +- .../ip/clk_wiz_0/clk_wiz_0_sim_netlist.v | 4 +- .../ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl | 4 +- .../sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v | 2 +- .../ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 2 +- .../ip/clk_wiz_0/clk_wiz_0.veo | 2 +- .../sim_scripts/clk_wiz_0/modelsim/README.txt | 2 +- .../clk_wiz_0/modelsim/clk_wiz_0.sh | 2 +- .../sim_scripts/clk_wiz_0/questa/README.txt | 2 +- .../sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh | 2 +- .../sim_scripts/clk_wiz_0/riviera/README.txt | 2 +- .../clk_wiz_0/riviera/clk_wiz_0.sh | 2 +- .../sim_scripts/clk_wiz_0/vcs/README.txt | 2 +- .../sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh | 2 +- .../sim_scripts/clk_wiz_0/xcelium/README.txt | 2 +- .../clk_wiz_0/xcelium/clk_wiz_0.sh | 2 +- .../sim_scripts/clk_wiz_0/xsim/README.txt | 2 +- .../sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh | 2 +- .../sources_1/ip/clk_wiz_0/clk_wiz_0.xci | 20 +++---- .../RISC-V-Scaffold-Basys3.xpr | 10 ++-- src/main/scala/RISCV/ALU.scala | 4 +- src/main/scala/RISCV/Main.scala | 3 +- 25 files changed, 71 insertions(+), 68 deletions(-) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v index 5bba0f4..6678366 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v @@ -54,7 +54,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo index f44f721..8e682f1 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo @@ -53,7 +53,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml index 775f901..8ed3b55 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -1314,11 +1314,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:7df132ee + 9:ad4d551b @@ -1333,11 +1333,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:7df132ee + 9:ad4d551b @@ -1352,11 +1352,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1371,11 +1371,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1386,7 +1386,7 @@ outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1397,7 +1397,7 @@ outputProductCRC - 9:ea0c8e5a + 9:7443706c @@ -1411,11 +1411,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:0455ee43 + 9:4527b5ca @@ -1429,11 +1429,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1444,7 +1444,7 @@ outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1460,11 +1460,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1478,11 +1478,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -2725,7 +2725,7 @@ C_OUTCLK_SUM_ROW2 - clk_out2__200.00000______0.000______50.0______114.829_____98.575 + clk_out2__25.00000______0.000______50.0______175.402_____98.575 C_OUTCLK_SUM_ROW3 @@ -2753,7 +2753,7 @@ C_CLKOUT2_REQUESTED_OUT_FREQ - 200.000 + 25 C_CLKOUT3_REQUESTED_OUT_FREQ @@ -2837,7 +2837,7 @@ C_CLKOUT2_OUT_FREQ - 200.00000 + 25.00000 C_CLKOUT3_OUT_FREQ @@ -3005,7 +3005,7 @@ C_MMCM_CLKOUT1_DIVIDE - 5 + 40 C_MMCM_CLKOUT2_DIVIDE @@ -3531,7 +3531,7 @@ C_DIVIDE2_AUTO - 0.125 + 1.0 C_DIVIDE3_AUTO @@ -3639,7 +3639,7 @@ C_CLKOUT1_ACTUAL_FREQ - 200.00000 + 25.00000 C_CLKOUT2_ACTUAL_FREQ @@ -4352,7 +4352,7 @@ CLKOUT2_REQUESTED_OUT_FREQ - 200.000 + 25 CLKOUT2_REQUESTED_PHASE @@ -4688,7 +4688,7 @@ MMCM_CLKOUT1_DIVIDE - 5 + 40 MMCM_CLKOUT1_DUTY_CYCLE @@ -4997,7 +4997,7 @@ CLKOUT2_JITTER Clkout2 Jitter - 114.829 + 175.402 CLKOUT2_PHASE_ERROR diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v index d319bf9..3bdbfa9 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v @@ -54,7 +54,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) @@ -134,7 +134,7 @@ wire clk_in2_clk_wiz_0; .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (5), + .CLKOUT1_DIVIDE (40), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v index b25e7bc..3dd5440 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -2,7 +2,7 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Fri Mar 13 02:38:01 2026 +// Date : Sun Apr 5 13:21:14 2026 // Host : arya running 64-bit EndeavourOS Linux // Command : write_verilog -force -mode funcsim -rename_top clk_wiz_0 -prefix // clk_wiz_0_ clk_wiz_0_sim_netlist.v @@ -111,7 +111,7 @@ module clk_wiz_0_clk_wiz_0_clk_wiz .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("FALSE"), - .CLKOUT1_DIVIDE(5), + .CLKOUT1_DIVIDE(40), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl index f3a5f3c..ac9abb0 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -2,7 +2,7 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Fri Mar 13 02:38:01 2026 +-- Date : Sun Apr 5 13:21:14 2026 -- Host : arya running 64-bit EndeavourOS Linux -- Command : write_vhdl -force -mode funcsim -rename_top clk_wiz_0 -prefix -- clk_wiz_0_ clk_wiz_0_sim_netlist.vhdl @@ -94,7 +94,7 @@ mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, - CLKOUT1_DIVIDE => 5, + CLKOUT1_DIVIDE => 40, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v index cc40900..22daff1 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -2,7 +2,7 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Fri Mar 13 02:38:01 2026 +// Date : Sun Apr 5 13:21:14 2026 // Host : arya running 64-bit EndeavourOS Linux // Command : write_verilog -force -mode synth_stub -rename_top clk_wiz_0 -prefix // clk_wiz_0_ clk_wiz_0_stub.v diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl index 5515e7b..de31cff 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -2,7 +2,7 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Fri Mar 13 02:38:01 2026 +-- Date : Sun Apr 5 13:21:14 2026 -- Host : arya running 64-bit EndeavourOS Linux -- Command : write_vhdl -force -mode synth_stub -rename_top clk_wiz_0 -prefix -- clk_wiz_0_ clk_wiz_0_stub.vhdl diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo index f44f721..8e682f1 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -53,7 +53,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh index 3f46253..3f07532 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh index 03f7951..3663c88 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh index 5d50237..fe45b67 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh index 0c8da79..2de1372 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh index 5472820..206ce22 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh index 9ac4270..3d4a5d5 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci index 537c13a..f9777fc 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -87,7 +87,7 @@ "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -171,7 +171,7 @@ "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT1_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -247,7 +247,7 @@ "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_JITTER": [ { "value": "175.402", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_JITTER": [ { "value": "114.829", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_JITTER": [ { "value": "175.402", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -339,14 +339,14 @@ "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__25.00000______0.000______50.0______175.402_____98.575", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__200.00000______0.000______50.0______114.829_____98.575", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__25.00000______0.000______50.0______175.402_____98.575", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -367,7 +367,7 @@ "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT1_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_OUT_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -409,7 +409,7 @@ "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "40.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -540,7 +540,7 @@ "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE2_AUTO": [ { "value": "0.125", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "1.0", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE3_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE4_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE5_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], @@ -567,7 +567,7 @@ "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], @@ -686,5 +686,5 @@ } } }, - "checksum": "2ec823c6" + "checksum": "eb66e59e" } \ No newline at end of file diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr index 4a9ee7c..b6531a3 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr @@ -66,12 +66,12 @@