diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v index 5bba0f4..6678366 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v @@ -54,7 +54,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo index f44f721..8e682f1 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo @@ -53,7 +53,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml index 775f901..8ed3b55 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -1314,11 +1314,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:7df132ee + 9:ad4d551b @@ -1333,11 +1333,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:7df132ee + 9:ad4d551b @@ -1352,11 +1352,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1371,11 +1371,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1386,7 +1386,7 @@ outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1397,7 +1397,7 @@ outputProductCRC - 9:ea0c8e5a + 9:7443706c @@ -1411,11 +1411,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:0455ee43 + 9:4527b5ca @@ -1429,11 +1429,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1444,7 +1444,7 @@ outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1460,11 +1460,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -1478,11 +1478,11 @@ GENtimestamp - Fri Mar 13 07:18:52 UTC 2026 + Sun Apr 05 17:27:05 UTC 2026 outputProductCRC - 9:6e49cf90 + 9:067c9c1a @@ -2725,7 +2725,7 @@ C_OUTCLK_SUM_ROW2 - clk_out2__200.00000______0.000______50.0______114.829_____98.575 + clk_out2__25.00000______0.000______50.0______175.402_____98.575 C_OUTCLK_SUM_ROW3 @@ -2753,7 +2753,7 @@ C_CLKOUT2_REQUESTED_OUT_FREQ - 200.000 + 25 C_CLKOUT3_REQUESTED_OUT_FREQ @@ -2837,7 +2837,7 @@ C_CLKOUT2_OUT_FREQ - 200.00000 + 25.00000 C_CLKOUT3_OUT_FREQ @@ -3005,7 +3005,7 @@ C_MMCM_CLKOUT1_DIVIDE - 5 + 40 C_MMCM_CLKOUT2_DIVIDE @@ -3531,7 +3531,7 @@ C_DIVIDE2_AUTO - 0.125 + 1.0 C_DIVIDE3_AUTO @@ -3639,7 +3639,7 @@ C_CLKOUT1_ACTUAL_FREQ - 200.00000 + 25.00000 C_CLKOUT2_ACTUAL_FREQ @@ -4352,7 +4352,7 @@ CLKOUT2_REQUESTED_OUT_FREQ - 200.000 + 25 CLKOUT2_REQUESTED_PHASE @@ -4688,7 +4688,7 @@ MMCM_CLKOUT1_DIVIDE - 5 + 40 MMCM_CLKOUT1_DUTY_CYCLE @@ -4997,7 +4997,7 @@ CLKOUT2_JITTER Clkout2 Jitter - 114.829 + 175.402 CLKOUT2_PHASE_ERROR diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v index d319bf9..3bdbfa9 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v @@ -54,7 +54,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) @@ -134,7 +134,7 @@ wire clk_in2_clk_wiz_0; .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (5), + .CLKOUT1_DIVIDE (40), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v index b25e7bc..3dd5440 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -2,7 +2,7 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Fri Mar 13 02:38:01 2026 +// Date : Sun Apr 5 13:21:14 2026 // Host : arya running 64-bit EndeavourOS Linux // Command : write_verilog -force -mode funcsim -rename_top clk_wiz_0 -prefix // clk_wiz_0_ clk_wiz_0_sim_netlist.v @@ -111,7 +111,7 @@ module clk_wiz_0_clk_wiz_0_clk_wiz .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("FALSE"), - .CLKOUT1_DIVIDE(5), + .CLKOUT1_DIVIDE(40), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl index f3a5f3c..ac9abb0 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -2,7 +2,7 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Fri Mar 13 02:38:01 2026 +-- Date : Sun Apr 5 13:21:14 2026 -- Host : arya running 64-bit EndeavourOS Linux -- Command : write_vhdl -force -mode funcsim -rename_top clk_wiz_0 -prefix -- clk_wiz_0_ clk_wiz_0_sim_netlist.vhdl @@ -94,7 +94,7 @@ mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, - CLKOUT1_DIVIDE => 5, + CLKOUT1_DIVIDE => 40, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v index cc40900..22daff1 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -2,7 +2,7 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Fri Mar 13 02:38:01 2026 +// Date : Sun Apr 5 13:21:14 2026 // Host : arya running 64-bit EndeavourOS Linux // Command : write_verilog -force -mode synth_stub -rename_top clk_wiz_0 -prefix // clk_wiz_0_ clk_wiz_0_stub.v diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl index 5515e7b..de31cff 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -2,7 +2,7 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Fri Mar 13 02:38:01 2026 +-- Date : Sun Apr 5 13:21:14 2026 -- Host : arya running 64-bit EndeavourOS Linux -- Command : write_vhdl -force -mode synth_stub -rename_top clk_wiz_0 -prefix -- clk_wiz_0_ clk_wiz_0_stub.vhdl diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo index f44f721..8e682f1 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -53,7 +53,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh index 3f46253..3f07532 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh index 03f7951..3663c88 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh index 5d50237..fe45b67 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh index 0c8da79..2de1372 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh index 5472820..206ce22 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt index 63015d2..77b73c8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 +# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh index 9ac4270..3d4a5d5 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 +# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci index 537c13a..f9777fc 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -87,7 +87,7 @@ "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -171,7 +171,7 @@ "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT1_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -247,7 +247,7 @@ "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_JITTER": [ { "value": "175.402", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_JITTER": [ { "value": "114.829", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_JITTER": [ { "value": "175.402", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -339,14 +339,14 @@ "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__25.00000______0.000______50.0______175.402_____98.575", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__200.00000______0.000______50.0______114.829_____98.575", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__25.00000______0.000______50.0______175.402_____98.575", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -367,7 +367,7 @@ "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT1_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_OUT_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -409,7 +409,7 @@ "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "40.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -540,7 +540,7 @@ "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE2_AUTO": [ { "value": "0.125", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "1.0", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE3_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE4_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE5_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], @@ -567,7 +567,7 @@ "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], @@ -686,5 +686,5 @@ } } }, - "checksum": "2ec823c6" + "checksum": "eb66e59e" } \ No newline at end of file diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr index 11d04dd..b6531a3 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr @@ -66,12 +66,12 @@