Roadmap

[unbtorsten]

Scope

• This meta-issue outlines ongoing and future development and documentation activities
• Tasks are loosely categorized as
  • static verification
  • dynamic verification
  • documentation (including content for slides)

Task List

• sdc/xdc parser #13 (preliminary code sufficient for now)
• Static verification: netlist contains same I/O pins as constraint file? cf. https://github.com/ERAS-Research/sanimut_fpga/pull/108 << move this to a general caveat/tests/static/
• Static verification: I/O pin constraints match net specification? #14
• Static verification: intra-bus skew limit #19
• Static verification: output pin current drive strength #16
• Static verification: voltage bank coherence #18
• ERAS-Research/sanimut_fpga#123
• Dyn. verification: throw errors/observations into cocotb-logging
• Dyn. verification: evaluate/visualize cocotb log
• Dyn. verification: monitor (based on cocotbext-axi? cocotb-inherent?) to verify valid syntax of incoming and outgoing data frames, related to (static) sanimut_check
• (Dyn. verification: evaluate/visualize cocotb log of passing frames?)
• Dyn. verification: conditional monitors (ensure processing by enforcing max. delay between inbound control frame and corresponding response frame or change on output pins) -- can cocotb keep track of and report global time/number of cycles between two events?
• Dyn. verification: analog frontend (iono_echo or similar)
• Dyn. verification, project-specific: basic communication interface #21
• Dyn. verification: combined digital + analog frontend, detect ADC overflow (and existing lack of processing of corresponding input pin)
• Organizational steps toward going public
  • Refactor folder and file structure
  • Rename ceveatenvironment to caveatbench
  • Consolidate and generalize bench-code to include as much as possible directly in caveat
    General overhaul and code structure refactoring for publication #30
    https://github.com/ERAS-Research/sanimut_fpga/pull/122
    • in/out signals with frame-dictionary/look-up table
    • call get...() for command/frame-information and plotting-mapping within caveat generic code
  • (Re)Create templates for static and dynamic tests
  • Confirm/review choice of open-source license (BSD-3)
  • Revise/edit main README.md
  • Package as Python package for ease of handling
    • How to install + use same files for continued development?
  • Revise requirements.txt
  • Checkout current private repo without history, transfer files to new public repo
    • Ensure project specific files such as echo.py are removed from repo beforehand
  • Add slides (to be) presented at FPGA conference as minimum documentation

Content for contribution to FPGA Conference Europe 2025

• Context of problem (2 slides: problem statement + high-level outline of how to solve)
• Introduction to cocotb and overview of how caveat uses and extends cocotb's capabilities
  • pytest
  • Pythonic configuration vs Makefile (1-2 slides, 1 example: side by side comparison of equivalent use)
  • Single test example (generic)
  • Extend example to parametrized test (generic)
  • Advanced interface based on cocotbext (by example of cocotbext-axi (1 slide, example)
• caveat example: parametrized Verilog module, generic analog simulation, parametrized tests (static? dynamic?)
• Demo emulated instrument (using open-source framework for testing "proprietary" design)
• Wrap up, hints on where to get and how to get started, invite collaboration/contributions

Task List (July 2025 and after)

• [ ]

[mferris03]

Dyn. verification: conditional monitors (ensure processing by enforcing max. delay between inbound control frame and corresponding response frame or change on output pins) -- can cocotb keep track of and report global time/number of cycles between two events?

Should be impementable via the Helper for the DUT